ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.28 CDP, CDP2
Coprocessor Data Processing tells a coprocessor to perform an operation that is independent of ARM core
registers and memory. If no coprocessor can execute the instruction, an Undefined Instruction exception is
generated.
This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture
and are free for use by the coprocessor instruction set designer. These fields are the opc1, opc2, CRd, CRn,
and CRm fields.
For more information about the coprocessors see Coprocessor support on page A2-68.
Encoding T1 / A1 ARMv6T2, ARMv7 for encoding T1
ARMv4*, ARMv5T*, ARMv6*, ARMv7 for encoding A1
CDP ,,,,,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 0 opc1 CRn CRd coproc opc2 0 CRm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 1 0 opc1 CRn CRd coproc opc2 0 CRm
if coproc == ‘101x’ then SEE “VFP instructions”;
cp = UInt(coproc);
Encoding T2 / A2 ARMv6T2, ARMv7 for encoding T2
ARMv5T*, ARMv6*, ARMv7 for encodingA2
CDP2 ,,,,,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 opc1 CRn CRd coproc opc2 0 CRm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0 opc1 CRn CRd coproc opc2 0 CRm
cp = UInt(coproc);
VFP instructions See VFP data-processing instructions on page A7-24
A8-68 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B