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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Register Index<br />

Register In a Description, see<br />

Data Memory Region Cacheability,<br />

pre-<strong>ARM</strong>v6<br />

Data Memory Region Extended Access<br />

Permissions, pre-<strong>ARM</strong>v6<br />

Data or unified Cache Lockdown,<br />

pre-<strong>ARM</strong>v7<br />

Data or unified Memory Region,<br />

pre-<strong>ARM</strong>v6<br />

Data or unified TLB Lockdown,<br />

pre-<strong>ARM</strong>v7<br />

c2, Memory Region Cacheability Registers (DCR <strong>and</strong> ICR) on<br />

page AppxH-44<br />

c5, Memory Region Extended Access Permissions Registers (DEAPR<br />

<strong>and</strong> IEAPR) on page AppxH-46<br />

c9, cache lockdown support on page AppxH-52<br />

c6, Memory Region registers (DMRR0-DMRR7 <strong>and</strong> IMRR0-IMRR7) on<br />

page AppxH-47<br />

c10, VMSA TLB lockdown support on page AppxH-59<br />

Data Region Access Control PMSA c6, Data Region Access Control Register (DRACR) on page B4-64<br />

Data Region Base Address PMSA c6, Data Region Base Address Register (DRBAR) on page B4-60<br />

Data Region Size <strong>and</strong> Enable PMSA c6, Data Region Size <strong>and</strong> Enable Register (DRSR) on page B4-62<br />

Data TCM Non-Secure Access Control,<br />

<strong>ARM</strong>v6<br />

Table K-1 Register index (continued)<br />

c9, TCM Non-Secure Access Control Registers, DTCM-NSACR <strong>and</strong><br />

ITCM-NSACR on page AppxG-51<br />

Data TCM Region, <strong>ARM</strong>v6 c9, TCM Region Registers (DTCMRR <strong>and</strong> ITCMRR) on page AppxG-47<br />

Data Transfer, Debug Host to Target Data Transfer Register (DBGDTRRX) on page C10-40<br />

Target to Host Data Transfer Register (DBGDTRTX) on page C10-43<br />

DBGAUTHSTATUS Authentication Status Register (DBGAUTHSTATUS) on page C10-96<br />

DBGBCR0 - DBGBCR15 Breakpoint Control Registers (DBGBCR) on page C10-49<br />

DBGBVR0 - DBGBVR15 Breakpoint Value Registers (DBGBVR) on page C10-48<br />

DBGCID0 - DBGCID3 Debug Component Identification Registers (DBGCID0 to DBGCID3)<br />

on page C10-102<br />

DBGCIDSR Context ID Sampling Register (DBGCIDSR) on page C10-39<br />

DBGCLAIMCLR Claim Tag Clear Register (DBGCLAIMCLR) on page C10-93<br />

DBGCLAIMSET Claim Tag Set Register (DBGCLAIMSET) on page C10-92<br />

DBGDEVID Debug Device ID Register (DBGDEVID) on page C10-6.<br />

DBGDEVTYPE Device Type Register (DBGDEVTYPE) on page C10-98<br />

AppxK-6 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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