ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

SDABORT_l, bit [6]
Debug Registers Reference
Sticky Synchronous Data Abort bit. This flag is set to 1 by any Data Abort exception that is
generated by a synchronous data abort when the processor is in Debug state. The possible
values of this bit are:
0 No Data Abort exception has been generated by a synchronous data abort since
the last time this bit was cleared to 0
1 A Data Abort exception has been generated by a synchronous data abort since
the last time this bit was cleared to 0.
The behavior of the DBGITR depends on the value of the SDABORT_l bit, see Instruction
Transfer Register (DBGITR) on page C10-46.
The method of clearing this flag to 0 depends on the version of the Debug architecture:
v7 Debug This flag is cleared to 0 only by writing to bit [2] of the DBGDRCR, see Debug
Run Control Register (DBGDRCR), v7 Debug only on page C10-29.
ARMv6 This flag is cleared to 0 when the external debugger reads the DBGDSCR.
Some aspects of the behavior of this flag depend on the version of the Debug architecture:
v7 Debug If the processor is in Non-debug state this flag is not set to 1 on a synchronous
Data Abort exception.
Leaving Debug state with this flag set to 1 causes UNPREDICTABLE behavior.
v6.1 Debug
If the processor is in Non-debug state this flag is not set to 1 on a synchronous
Data Abort exception.
v6 Debug If the processor is in Non-debug state, the value of this flag is UNKNOWN.
For more information, see Exceptions in Debug state on page C5-20.
MOE, bits [5:2]
Method of Debug Entry field. The permitted values of this field depend on the Debug
architecture. For details of this field see Method of Debug entry on page C10-26.
RESTARTED, bit [1]
Processor Restarted bit. The possible values of this bit are:
0 The processor is exiting Debug state. This bit only reads as 0 between receiving
a restart request, and restarting Non-debug state operation.
1 The processor has exited Debug state. This bit remains set to 1 if the processor
re-enters Debug state.
After making a restart request, the debugger can poll this bit until it is set to 1. At that point
it knows that the restart request has taken effect and the processor has exited Debug state.
Note
Polling the HALTED bit until it is set to 0 is not safe because the processor could re-enter
Debug state as a result of another debug event before the debugger samples the DBGDSCR.
See Chapter C5 Debug State for a definition of Debug state.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-19