ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

G.7.14 c9, Cache lockdown support
ARMv6 Differences
One problem with caches is that although they normally improve average access time to data and
instructions, they usually increase the worst-case access time. This occurs for a number of reasons,
including:
There is a delay before the system determines that a cache miss has occurred and starts the main
memory access.
If a Write-Back cache is being used, there might be an extra delay because of the requirement to store
the contents of the cache line that is being reallocated.
A whole cache line is loaded from main memory, not only the data requested by the ARM processor.
In real-time applications, this increase in the worst-case access time can be significant.
Cache lockdown is an optional feature designed to alleviate this. It enables critical code and data, for
example high priority interrupt routines and the data they access, to be loaded into the cache in such a way
that the cache lines containing them are not subsequently reallocated. This ensures that all subsequent
accesses to the code and data concerned are cache hits and therefore complete as quickly as possible.
From ARMv7, cache lockdown is IMPLEMENTATION DEFINED with no recommended formats or
mechanisms on how it is achieved other than reserved CP15 register space. See Cache lockdown on
page B2-8 and CP15 c9, Cache and TCM lockdown registers and performance monitors on page B3-141.
ARMv4 and ARMv5 specify four formats for the cache lockdown mechanism, known as Format A, Format
B, Format C, and Format D. The Cache Type Register contains information on the lockdown mechanism
adopted. See c0, Cache Type Register (CTR) on page AppxH-35. Formats A, B, and C all operate on cache
ways. Format D is a cache entry locking mechanism.
ARMv6 cache lockdown support must comply with Format C or Format D. For more information, see c9,
cache lockdown support on page AppxH-52.
Note
A Format D implementation must use the CP15 lockdown operations with the CRm == {c5,c6} encodings,
and not the alternative encodings with CRm == {c1,c2}.
Interaction with CP15 c7 operations
Cache lockdown only prevents the normal replacement strategy used on cache misses from choosing to
reallocate cache lines in the locked-down region. CP15 c7 operations that invalidate, clean, or clean and
invalidate cache contents affect locked-down cache lines as normal. If invalidate operations are used, you
must ensure that they do not use virtual addresses or cache set/way combinations that affect the locked-down
cache lines. Otherwise, if it is difficult to avoid affecting the locked-down cache lines, repeat the cache
lockdown procedure afterwards.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxG-45