ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Instruction Set Encoding
A5.2.11 MSR (immediate), and hints
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 1 1 0 op 1 0 op1 op2
Table A5-13 shows the allocation of encodings in this space.
Other encodings in this space are unallocated hints. They execute as NOPs, but software must not use them.
Table A5-13 MSR (immediate), and hints
op op1 op2 Instruction See Variant
0 0000 00000000 No Operation hint NOP on page A8-222 v6K, v6T2
00000001 Yield hint YIELD on page A8-812 v6K
00000010 Wait For Event hint WFE on page A8-808 v6K
00000011 Wait For Interrupt hint WFI on page A8-810 v6K
00000100 Send Event hint SEV on page A8-316 v6K
1111xxxx Debug hint DBG on page A8-88 v7
0100 - Move to Special Register,
1x00 -
application level
xx01 - Move to Special Register, system
xx1x -
level
1 - - Move to Special Register, system
level
MSR (immediate) on page A8-208 All
MSR (immediate) on page B6-12 All
MSR (immediate) on page B6-12 All
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A5-17