ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.317 VLD4 (single 4-element structure to one lane)
This instruction loads one 4-element structure from memory into corresponding elements of four registers.
Elements of the registers that are not loaded are unchanged. For details of the addressing mode see Advanced
SIMD addressing mode on page A7-30.
Encoding T1 / A1 Advanced SIMD
VLD4. , [{@}]{!}
VLD4. , [{@}],
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 1 D 1 0 Rn Vd size 1 1 index_align Rm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 1 1 index_align Rm
if size == ‘11’ then SEE VLD4 (single 4-element structure to all lanes);
case size of
when ‘00’
ebytes = 1; esize = 8; index = UInt(index_align); inc = 1;
alignment = if index_align == ‘0’ then 1 else 4;
when ‘01’
ebytes = 2; esize = 16; index = UInt(index_align);
inc = if index_align == ‘0’ then 1 else 2;
alignment = if index_align == ‘0’ then 1 else 8;
when ‘10’
if index_align == ‘11’ then UNDEFINED;
ebytes = 4; esize = 32; index = UInt(index_align);
inc = if index_align == ‘0’ then 1 else 2;
alignment = if index_align == ‘00’ then 1 else 4 31 then UNPREDICTABLE;
Assembler syntax
VLD4. , [{@}] Rm = ’1111’
VLD4. , [{@}]! Rm = ’1101’
VLD4. , [{@}], Rm = other values
where:
See Standard assembler syntax fields on page A8-7. An ARM VLD4 instruction must be
unconditional.
The data size. It must be one of:
8 encoded as size = 0b00
16 encoded as size = 0b01
32 encoded as size = 0b10.
A8-622 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B