ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

DminLine, bits [19:16]
Bit [15] RAO.
Bits [14:4] RAZ.
IminLine, bits [3:0]
Accessing the CTR
Values greater than 0b1001 are reserved.
Protected Memory System Architecture (PMSA)
Log2 of the number of words in the smallest cache line of all the data caches and unified
caches that are controlled by the processor.
Log2 of the number of words in the smallest cache line of all the instruction caches that are
controlled by the processor.
To access the CTR you read the CP15 registers with set to 0, set to c0, set to c0, and
set to 1. For example
MRC p15,0,,c0,c0,1 ; Read CP15 Cache Type Register
B4.6.8 c0, TCM Type Register (TCMTR)
The TCM Type Register, TCMTR, provides information about the implementation of the TCM.
The TCMTR is:
a 32-bit read-only register
accessible only in privileged modes.
From ARMv7:the
TCMTR must be implemented
when the ARMv7 format is used, the meaning of register bits [28:0] is IMPLEMENTATION DEFINED
the ARMv6 format of the TCM Type Register remains a valid usage model
if no TCMs are implemented the ARMv6 format must be used to indicate zero-sized TCMs.
The ARMv7 format of the TCMTR is:
31 29 28 0
1 0 0 IMPLEMENTATION DEFINED
Bits [31:29] Set to 0b100 for the ARMv7 register format. Set to 0b000 for the format used in ARMv6
and earlier.
Bits [28:0] IMPLEMENTATION DEFINED in the ARMv7 register format.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-35