ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv4 and ARMv5 Differences
c2, Memory Region Cacheability Registers (DCR and ICR)
The two Memory Region Cacheability Registers are:
The Data or unified Cacheability Register, DCR.
The Instruction Cacheability Register, ICR. The ICR is implemented only when the processor
implements separate data and instruction memory protection region definitions.
A Memory Region Cacheability Registers holds a Cacheability bit, C, for each of the eight memory
protection regions.
The format of a Memory Region Cacheability Register is:
31 8 7 6 5 4 3 2 1 0
Reserved C7 C6 C5 C4 C3 C2 C1 C0
Bits [31:8] Reserved. UNK/SBZP.
Cn, bit [n], for n = 0 to 7
Cacheability bit, C, for memory protection region n.
Accessing the Memory Region Cacheability Registers
To access the Memory Region Cacheability Registers you read or write the CP15 registers with set
to 0, set to c2, set to c0, and set to:
0 for the DCR
1 for the IPR.
For example:
MRC p15,0,,c2,c0,0 ; Read CP15 Data or unified Region Cacheability Register
MCR p15,0,,c2,c0,0 ; Write CP15 Data or unified Region Cacheability Register
MRC p15,0,,c2,c0,1 ; Read CP15 Instruction Region Cacheability Register
MCR p15,0,,c2,c0,1 ; Write CP15 Instruction Region Cacheability Register
c3, Memory Region Bufferability Register (DBR)
The Memory Region Bufferability Register, DBR, holds Bufferability bit, B, for each of the eight data or
unified memory protection regions.
Only data accesses are bufferable and therefore there is only a single Memory Region Bufferability Register,
regardless of whether the implementation has a single set of protection regions, or separate protection region
definitions for instruction and data accesses.
The format of the Memory Region Bufferability Register is:
31 8 7 6 5 4 3 2 1 0
Reserved B7 B6 B5 B4 B3 B2 B1 B0
Bits [31:8] Reserved. UNK/SBZP.
AppxH-44 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B