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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Application Level Programmers’ Model<br />

Pseudocode details of ITSTATE operations<br />

ITSTATE advances after normal execution of an IT block instruction. This is described by the ITAdvance()<br />

pseudocode function:<br />

// ITAdvance()<br />

// ===========<br />

ITAdvance()<br />

if ITSTATE == ‘000’ then<br />

ITSTATE.IT = ‘00000000’;<br />

else<br />

ITSTATE.IT = LSL(ITSTATE.IT, 1);<br />

The following functions test whether the current instruction is in an IT block, <strong>and</strong> whether it is the last<br />

instruction of an IT block:<br />

// InITBlock()<br />

// ===========<br />

boolean InITBlock()<br />

return (ITSTATE.IT != ‘0000’);<br />

// LastInITBlock()<br />

// ===============<br />

IT bits a<br />

[7:5] [4] [3] [2] [1] [0]<br />

boolean LastInITBlock()<br />

return (ITSTATE.IT == ‘1000’);<br />

Table A2-2 Effect of IT execution state bits<br />

a. Combinations of the IT bits not shown in this table are reserved.<br />

A2-18 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B<br />

Note<br />

cond_base P1 P2 P3 P4 1 Entry point for 4-instruction IT block<br />

cond_base P1 P2 P3 1 0 Entry point for 3-instruction IT block<br />

cond_base P1 P2 1 0 0 Entry point for 2-instruction IT block<br />

cond_base P1 1 0 0 0 Entry point for 1-instruction IT block<br />

000 0 0 0 0 0 Normal execution, not in an IT block

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