ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
Uses JEP Code, bit [3]
For an ARMv7 implementation this bit must be one, indicating that the Peripheral ID uses
a JEP 106 Identity Code.
JEP Identity Code[6:4], bits [2:0]
DBGPID3
Bits [6:4] of the IMPLEMENTATION DEFINED JEP Identity Code.
For a device designed by ARM the JEP Identity Code is 0x3B and therefore this field is
0b011.
DBGPID3 is debug register 1019 at offset 0xFEC. Its format is:
Bits [31:8] Reserved, RAZ.
RevAnd, bits [7:4]
Customer modified, bits [3:0]
DBGPID4
The IMPLEMENTATION DEFINED manufacturing revision number for the device.
An IMPLEMENTATION DEFINED value that indicates an endorsed modification to the device.
If the system designer cannot modify the RTL supplied by the processor designer then this
field is RAZ.
DBGPID4 is debug register 1012 at offset 0xFD0. Its format is:
Bits [31:8] Reserved, RAZ.
4KB count, bits [7:4]
This field is RAZ for all ARMv7 implementations.
JEP 106 Continuation code, bits [3:0]
The IMPLEMENTATION DEFINED JEP 106 Continuation code.
For a device designed by ARM this field is 0x4.
C10.8.10 Debug Component Identification Registers (DBGCID0 to DBGCID3)
The Debug Component Identification Registers identify the processor as an ARM Debug Interface v5
Component. For more information, see the ARM Debug Interface v5 Architecture Specification.
The Debug Component Identification Registers:
are debug registers 1020-1023, at offsets 0xFF0-0xFFC
are read-only registers
C10-102 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B