ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Recommended External Debug Interface
DBGSELFADDR specifies bits [31:12] of the two’s complement signed offset from the ROM Table
physical address to the physical address where the debug registers are Memory-mapped. This is a
configuration input. It must either:
be a tie-off
change only while the processor is in reset.
If there is no ROM Table, DBGROMADDR must be configured as described in the section
DBGROMADDR and DBGROMADDRV on page AppxA-10, and DBGSELFADDR must be tied off to
zero with DBGSELFADDRV tied HIGH.
DBGSELFADDRV is the valid signal for DBGSELFADDR. If the offset cannot be determined,
DBGSELFADDR must be tied off to zero and DBGSELFADDRV tied LOW.
A.1.10 DBGSWENABLE
DBGSWENABLE is not required in v6 Debug and v6.1 Debug.
In v7 Debug, DBGSWENABLE is driven by the Debug Access Port. For details see the ARM Debug
Interface v5 Architecture Specification.
DBGSWENABLE is an active-HIGH signal that must be asserted to enable system access to the debug
register file. That is, if deasserted it prevents access through the memory-mapped and Extended CP14
interfaces. This gives the debugger full control over the debug registers in the processor.
When this signal is deasserted by the debugger by a means that is IMPLEMENTATION DEFINED,
memory-mapped interface accesses return an error response and most Extended CP14 operations become
UNDEFINED instructions. See CP14 debug registers access permissions on page C6-36 and Permission
summaries for memory-mapped and external debug interfaces on page C6-45.
In the ARM Debug Interface v5, DBGSWENABLE is asserted by setting the DbgSwEnable control bit in
the access port Control Status Word Register (CSW) to 1. For the memory-mapped interface, when the
DbgSwEnable control bit is set to 0 the generation of slave-generated errors is a function of the ADIv5
Debug Access Port, and therefore the processor ignores the DBGSWENABLE signal for the
memory-mapped interface. For details see the ARM Debug Interface v5 Architecture Specification.
The DBGSWENABLE signal has no effect on accesses through the external debug interface.
Normally, the DBGSWENABLE signal must be asserted at debug logic reset and deasserted under
debugger control.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxA-11