ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The SMC instruction is added as part of the Security Extensions.
ARMv6 Differences
The CLREX, LDREXB, LDREXD, LDREXH, NOP, SEV, STREXB, STREXD, STREXH, WFE, WFI, and YIELD instructions are added
with the enhanced kernel support as part of ARMv6K.
New ARM instructions in ARMv6T2
ARMv6T2 adds the following ARM instructions:
BFC, BFI, LDRHT, LDRSBT, LDRSHT, MLS, MOVT, RBIT, SBFX, STRHT, and UBFX.
Instructions that are only in the ARM instruction set in ARMv6T2
The following ARM instructions have no Thumb equivalents in ARMv6T2:
register-shifted forms of the ADC, ADD, AND, BIC, CMN, CMP, EOR, MVN, ORR, RSB, SBC, SUB, TEQ, and TST
instructions
all forms of the RSC instruction
LDMDA, LDMIB, STMDA, and STMIB
SWP and SWPB.
ARM instructions introduced in ARMv7
Table G-2 ARM instruction changes in ARMv6 (continued)
Instruction ARMv6 change
UQSUB8, UQSUB16, UQSAX Introduced
USAD8, USADA8 Introduced
USAT, USAT16 Introduced
USUB8, USUB16, USAX Introduced
UXTAB, UXTAB16, UXTAH Introduced
UXTB, UXTB16, UXTH Introduced
The DMB, DSB, ISB, PLI, SDIV, and UDIV instructions are added in ARMv7 and are not present in any form in
ARMv6. The SDIV and UDIV instructions are not present in ARMv7-A.
The DBG hint instruction is added in ARMv7. It is UNDEFINED in the ARMv6 base architecture, and executes
as a NOP instruction in ARMv6K and ARMv6T2.
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