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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Assembler syntax<br />

VDUP. , Encoded as Q = 1<br />

VDUP. , Encoded as Q = 0<br />

where:<br />

Instruction Details<br />

See St<strong>and</strong>ard assembler syntax fields on page A8-7. An <strong>ARM</strong> VDUP instruction must be<br />

unconditional.<br />

The data size. It must be one of:<br />

8 Encoded as imm4 = '1'. imm4 encodes the index [x] of the scalar.<br />

16 Encoded as imm4 = '10'. imm4 encodes the index [x] of the scalar.<br />

32 Encoded as imm4 = '100'. imm4 encodes the index [x] of the scalar.<br />

The destination vector for a quadword operation.<br />

The destination vector for a doubleword operation.<br />

The scalar. For details of how [x] is encoded, see the description of .<br />

Operation<br />

if ConditionPassed() then<br />

EncodingSpecificOperations(); CheckAdvSIMDEnabled();<br />

scalar = Elem[D[m],index,esize];<br />

for r = 0 to regs-1<br />

for e = 0 to elements-1<br />

Elem[D[d+r],e,esize] = scalar;<br />

Exceptions<br />

Undefined Instruction.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. A8-593

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