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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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<strong>ARM</strong>v6 Differences<br />

G.4.2 Thumb instruction set support<br />

<strong>ARM</strong>v6 includes all the Thumb instructions present in <strong>ARM</strong>v5TE, see Thumb instruction set support on<br />

page AppxH-15. the 16-bit Thumb instructions added in the <strong>ARM</strong>v6 base architecture are:<br />

CPS<br />

CPY<br />

REV, REV16, REVSH<br />

SETEND<br />

SXTB, SXTH<br />

UXTB, UXTH.<br />

Thumb instruction set <strong>and</strong> <strong>ARM</strong>v6T2<br />

From the <strong>ARM</strong>v6T2 version of the Thumb instruction set:<br />

The Thumb instruction set provides 16-bit <strong>and</strong> 32-bit instructions that are executed in Thumb state.<br />

Most forms of <strong>ARM</strong> instructions have an equivalent Thumb encoding. Instructions that are only in<br />

the <strong>ARM</strong> instruction set in <strong>ARM</strong>v6T2 on page AppxG-13 lists the exceptions to this in <strong>ARM</strong>v6T2.<br />

The CBZ, CBNZ, <strong>and</strong> IT instructions are only in the Thumb instruction set <strong>and</strong> are introduced in <strong>ARM</strong>v6T2.<br />

Before <strong>ARM</strong>v6T2, a BL or BLX (immediate) Thumb instruction can be executed as a pair of 16-bit<br />

instructions, rather than as a single 32-bit instruction. For more information, see BL <strong>and</strong> BLX (immediate)<br />

instructions, before <strong>ARM</strong>v6T2 on page AppxG-4. From <strong>ARM</strong>v6T2 these instructions are always executed<br />

as a single 32-bit instruction.<br />

From <strong>ARM</strong>v6T2, the branch range of the BL <strong>and</strong> BLX (immediate) instructions is increased from<br />

approximately ±4MB to approximately ±16MB.<br />

Thumb instructions introduced in <strong>ARM</strong>v7<br />

The CLREX, LDREXB, LDREXD, LDREXH, STREXB, STREXD, <strong>and</strong> STREXH instructions are added to the Thumb instruction<br />

set in <strong>ARM</strong>v7. They are Thumb equivalents to the <strong>ARM</strong> instructions added in <strong>ARM</strong>v6K. These instructions<br />

are UNDEFINED in <strong>ARM</strong>v6T2.<br />

The DBG, SEV, WFE, WFI, <strong>and</strong> YIELD hint instructions are added in <strong>ARM</strong>v7. They execute as NOP instructions in<br />

<strong>ARM</strong>v6T2. The 16-bit encodings of the SEV, WFE, WFI, <strong>and</strong> YIELD instructions are UNDEFINED in the <strong>ARM</strong>v6<br />

base architecture <strong>and</strong> in <strong>ARM</strong>v6K.<br />

G.4.3 System level instruction set support<br />

The system instructions supported in <strong>ARM</strong>v6 are the same as those listed for <strong>ARM</strong>v7 in Alphabetical list<br />

of instructions on page B6-2:<br />

the SMC instruction only applies to the Security Extensions<br />

the VMRS <strong>and</strong> VMSR instructions only apply to VFP.<br />

AppxG-14 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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