ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

State1, bits [7:4]
The CPUID Identification Scheme
Thumb instruction set support. Permitted values are:
0b0000 No support for Thumb instruction set.
0b0001 Support for Thumb encoding before the introduction of Thumb-2 technology:
all instructions are 16-bit
a BL or BLX is a pair of 16-bit instructions
32-bit instructions other than BL and BLX cannot be encoded.
0b0010 Reserved.
0b0011 Support for Thumb encoding after the introduction of Thumb-2 technology, and
for all 16-bit and 32-bit Thumb basic instructions.
State0, bits [3:0]
ARM instruction set support. Permitted values are:
0b0000 No support for ARM instruction set.
0b0001 Support for ARM instruction set.
c0, Processor Feature Register 1 (ID_PFR1)
The format of ID_PFR1 is:
31 13 12 8 7 4 3 0
Bits [31:12] Reserved, RAZ.
Reserved, RAZ
M profile programmers’ model, bits [11:8]
M profile programmers’ model
Permitted values are:
0b0000 Not supported.
0b0010 Support for two-stack programmers’ model.
The value of 0b0001 is reserved.
Security
Extensions
Programmers’ model
Security Extensions, bits [7:4]
Permitted values are:
0b0000 Not supported.
0b0001 Support for the Security Extensions.
This includes support for Monitor mode and the SMC instruction.
0b0010 As for 0b0001, and adds the ability to set the NSACR.RFR bit.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B5-5