ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Advanced SIMD and VFP Instruction Encoding
A7.9 64-bit transfers between ARM core and extension registers
If T == 1 in the Thumb encoding or cond == 0b1111 in the ARM encoding, the instruction is UNDEFINED.
Otherwise, the allocation of encodings in this space is shown in Table A7-23. Other encodings in this space
are UNDEFINED.
These instructions are MRRC and MCRR instructions for coprocessors 10 and 11.
Thumb encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 T 1 1 0 0 0 1 0 1 0 1 C op
ARM encoding
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 0 0 0 1 0 1 0 1 C op
C op Instruction
Table A7-23 8-bit, 16-bit and 32-bit data transfer instructions
0 00x1 VMOV (between two ARM core registers and two single-precision registers) on page A8-650
1 00x1 VMOV (between two ARM core registers and a doubleword extension register) on page A8-652
A7-32 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B