ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instructions for CP14 and CP15
Debug State
This subsection describes the coprocessor instructions for the internal coprocessors CP14 and CP15.
The two groups of registers provided by CP14 are:
The CP14 debug registers, accessed by MCR and MRC instructions with == 0b000. Some of these
registers can also be accessed by CP14 LDC and STC instructions.
The CP14 non-debug registers, accessed by MCR and MRC instructions with != 0b000. These
include the trace registers.
Accesses to CP14 and CP15 are as follows:
Instructions that access CP14 or CP15 registers that are permitted (not UNDEFINED) in User mode
when in Non-debug state, are always permitted in Debug state.
Instructions that access CP14 debug registers that are permitted (not UNDEFINED) in privileged modes
when in Non-debug state are permitted in Debug state, regardless of the debug authentication and the
processor mode and security state.
If Secure User halting debug is supported, ARM recommends that certain CP15 instructions that a
debugger requires to maintain memory coherency are permitted in Debug state regardless of debug
permissions and the processor mode, see Access to specific cache management functions in Debug
state on page C5-25.
If the processor is in a privileged mode or the debugger can write to the CPSR.M bits to change to a
privileged mode, then instructions that access CP14 or CP15 registers that are permitted (not
UNDEFINED) in privileged modes when in Non-debug state are permitted in Debug state. If the
processor is in User mode there is no requirement to change to a privileged mode first.
Note
— Two particular cases are where Security Extensions are not implemented and where Secure
User halting debug is not supported. In these cases the CPSR.M bits can always be changed to
a privileged mode and, therefore, the debugger is able to access all CP14 and CP15 registers
at all times.
— Except for accesses to the Baseline CP14 debug registers, ARM deprecates accessing any
CP14 or CP15 register from User mode in Debug state if that register cannot be accessed from
User mode in Non-debug state.
In every case, permissions to access CP14 and CP15 registers while in Debug state are never greater
than the permissions granted to any privileged mode when in Non-debug state in the current security
state.
If the processor is in Secure User mode and the debugger cannot write to the CPSR.M bits to change
to a privileged mode, then any instruction that accesses a CP14 non-debug register or a CP15 register
is not permitted (UNDEFINED) in Debug state if it is not permitted in Secure User mode in Non-debug
state.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C5-17