ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Thumb Instruction Set Encoding
A6.3 32-bit Thumb instruction encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 op1 op2 op
If op1 == 0b00, a 16-bit instruction is encoded, see 16-bit Thumb instruction encoding on page A6-6.
Table A6-9 shows the allocation of encodings in this space.
op1 op2 op Instruction class, see
01 00xx0xx - Load/store multiple on page A6-23
Table A6-9 32-bit Thumb instruction encoding
00xx1xx - Load/store dual, load/store exclusive, table branch on page A6-24
01xxxxx - Data-processing (shifted register) on page A6-31
1xxxxxx - Coprocessor instructions on page A6-40
10 x0xxxxx 0 Data-processing (modified immediate) on page A6-15
x1xxxxx 0 Data-processing (plain binary immediate) on page A6-19
- 1 Branches and miscellaneous control on page A6-20
11 000xxx0 - Store single data item on page A6-30
001xxx0 - Advanced SIMD element or structure load/store instructions on page A7-27
00xx001 - Load byte, memory hints on page A6-28
00xx011 - Load halfword, memory hints on page A6-26
00xx101 - Load word on page A6-25
00xx111 - UNDEFINED
010xxxx - Data-processing (register) on page A6-33
0110xxx - Multiply, multiply accumulate, and absolute difference on page A6-38
0111xxx - Long multiply, long multiply accumulate, and divide on page A6-39
1xxxxxx - Coprocessor instructions on page A6-40
A6-14 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B