ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The Instruction Sets
A4.4.7 Parallel addition and subtraction instructions
These instructions perform additions and subtractions on the values of two registers and write the result to
a destination register, treating the register values as sets of two halfwords or four bytes. They are available
in ARMv6 and above.
These instructions consist of a prefix followed by a main instruction mnemonic. The prefixes are as follows:
S Signed arithmetic modulo 2 8 or 2 16.
Q Signed saturating arithmetic.
SH Signed arithmetic, halving the results.
U Unsigned arithmetic modulo 2 8 or 2 16.
UQ Unsigned saturating arithmetic.
UH Unsigned arithmetic, halving the results.
The main instruction mnemonics are as follows:
ADD16 Adds the top halfwords of two operands to form the top halfword of the result, and the
bottom halfwords of the same two operands to form the bottom halfword of the result.
ASX Exchanges halfwords of the second operand, and then adds top halfwords and subtracts
bottom halfwords.
SAX Exchanges halfwords of the second operand, and then subtracts top halfwords and adds
bottom halfwords.
SUB16 Subtracts each halfword of the second operand from the corresponding halfword of the first
operand to form the corresponding halfword of the result.
ADD8 Adds each byte of the second operand to the corresponding byte of the first operand to form
the corresponding byte of the result.
SUB8 Subtracts each byte of the second operand from the corresponding byte of the first operand
to form the corresponding byte of the result.
The instruction set permits all 36 combinations of prefix and main instruction operand.
See also Advanced SIMD parallel addition and subtraction on page A4-31.
A4-16 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B