ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

new_spsr_value = CPSR;
The System Level Programmers’ Model
// Determine whether this is an external abort to be trapped to Monitor mode.
trap_to_monitor = HaveSecurityExt() && SCR.EA == ‘1’ && IsExternalAbort();
// Enter Abort (‘10111’) or Monitor (‘10110’) mode, and ensure Secure state if
// initially in Monitor mode. This affects the banked versions of various registers
// accessed later in the code.
if CPSR.M == ‘10110’ then SCR.NS = ‘0’;
CPSR.M = if trap_to_monitor then ‘10110’ else ‘10111’;
// Write return information to registers, and make further CPSR changes: IRQs disabled,
// other interrupts disabled if appropriate, IT state reset, instruction set and
// endianness to SCTLR-configured values.
SPSR[] = new_spsr_value;
R[14] = new_lr_value;
CPSR.I = ‘1’;
if trap_to_monitor then
CPSR.F = ‘1’; CPSR.A = ‘1’;
else
if !HaveSecurityExt() || SCR.NS == ‘0’ || SCR.AW == ‘1’ then CPSR.A = ‘1’;
CPSR.IT = ‘00000000’;
CPSR.J = ‘0’; CPSR.T = SCTLR.TE; // TE=0: ARM, TE=1: Thumb
CPSR.E = SCTLR.EE; // EE=0: little-endian, EE=1: big-endian
// Branch to correct Prefetch Abort vector.
if trap_to_monitor then
BranchTo(MVBAR + 12);
else
BranchTo(ExcVectorBase() + 12);
The preferred exception return from a Prefetch Abort exception is a return to the aborted instruction. Use
the LR and SPSR values generated by the exception entry to produce this return by using an exception return
instruction with a subtraction of 4.
For more information, see Exception return on page B1-38.
B1.6.15 Data Abort exception
A Data Abort exception can be generated by:
A synchronous abort on a data read or write memory access. Exception entry is synchronous to the
instruction that generated the memory access.
An asynchronous abort. The memory access that caused the abort can be any of:
— a data read or write access
— an instruction fetch or prefetch
— in a VMSA memory system, a translation table access.
Exception entry occurs asynchronously. It is similar to an interrupt, but uses either Abort mode or
Monitor mode, and the associated banked registers. Setting the CPSR.A bit prevents asynchronous
aborts from occurring.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B1-55