ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
B4.6.29 CP15 c9, Cache and TCM lockdown registers and performance monitors
Some CP15 c9 register encodings are reserved for IMPLEMENTATION DEFINED memory system functions, in
particular:
cache control, including lockdown
TCM control, including lockdown
branch predictor control.
Additional CP15 c9 encodings are reserved for performance monitors. These encodings fall into two groups:
the optional performance monitors described in Chapter C9 Performance Monitors
additional IMPLEMENTATION DEFINED performance monitors.
The reserved encodings permit implementations that are compatible with previous versions of the ARM
architecture, in particular with the ARMv6 requirements. Figure B4-11 shows the permitted CP15 c9
register encodings.
CRn opc1 CRm opc2
c9 {0-7} {c0-c2} {0-7} ‡ Reserved for Branch Predictor, Cache and TCM operations
{c5-c8} {0-7} ‡ Reserved for Branch Predictor, Cache and TCM operations
{c12-c14} {0-7} Reserved for ARM-recommended Performance Monitors
c15 {0-7} ‡ Reserved for IMPLEMENTATION DEFINED Performance Monitors
Read-only Read/Write
Write-only
‡ Access depends on the operation
Figure B4-11 Permitted CP15 c9 register encodings
All CP15 c9 encodings not shown in Figure B4-11 are UNPREDICTABLE, see Unallocated CP15 encodings
on page B4-27.
In ARMv6, CP15 c9 provides cache lockdown functions. With the ARMv7 abstraction of the hierarchical
memory model, for CP15 c9:
All encodings with CRm = {c0-c2, c5-c8} are reserved for IMPLEMENTATION DEFINED cache, branch
predictor and TCM operations.
This reservation enables the implementation of a scheme that is backwards compatible with ARMv6.
For details of the ARMv6 implementation see c9, Cache lockdown support on page AppxG-45.
All encodings with CRm = {c12-c14} are reserved for the optional performance monitors that are
defined in Chapter C9 Performance Monitors.
All encodings with CRm = c15 are reserved for IMPLEMENTATION DEFINED performance monitoring
features.
B4.6.30 CP15 c10, Not used on a PMSA implementation
CP15 c10 is not used on an ARMv7-R implementation, see Unallocated CP15 encodings on page B4-27.
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