ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARMv4 and ARMv5 Differences
Memory access sequence
When the ARM processor generates a memory access, the MPU compares the memory address with the
programmed memory regions as follows:
If a matching memory region is not found, a memory abort is signaled to the processor.
If a matching memory region is found, the region information is used as follows:
— The access permission bits are used to determine whether the access is permitted. If the access
is not permitted, the MPU signals a memory abort. Otherwise, the access can proceed.
— The memory region attributes are used to determine the access attributes, for example cached
or non-cached, as described in Memory type support on page AppxH-10.
Note
When a Permission fault occurs, there is no fault status information provision for PMSA in ARMv4 or
ARMv5. The CP15 registers FSR and FAR are only available in implementations with VMSA support.
Overlapping regions
The Protection Unit can be programmed with two or more overlapping regions. When overlapping regions
are programmed, a fixed priority scheme is applied to determine the region whose attributes are applied to
the memory access.
Attributes for region 7 take highest priority and those for region 0 take lowest priority. For example:
Data region 2 is programmed to be 4KB in size, starting from address 0x3000 with AP == 0b010
(privileged modes full access, User mode read-only).
Data region 1 is programmed to be 16KB in size, starting from address 0x0 with AP == 0b001
(privileged mode access only).
When the processor performs a data load from address 0x3010 while in User mode, the address falls into both
region 1 and region 2. Because there is a clash, the attributes associated with region 2 are applied. In this
case, the load would not abort.
Background region
Overlapping regions increase the flexibility of how regions can be mapped onto physical memory devices
in the system. The overlapping properties can also be used to specify a background region. For example,
assume a number of physical memory areas sparsely distributed across the 4GB address space. If only these
regions are configured, any access outside the defined sparse address space aborts. You can override this
behavior by programming region 0 to be a 4GB background region. In this case, if the address does not fall
into any of the other regions, the access is controlled by the attributes specified for region 0.
AppxH-30 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B