ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.104 MSR (register)
Move to Special Register from ARM core register moves selected bits of a general-purpose register to the
APSR.
For details of system level use of this instruction, see MSR (register) on page B6-14.
Encoding T1 ARMv6T2, ARMv7
MSR ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 0 0 0 Rn 1 0 (0) 0 mask 0 0 (0)(0)(0)(0)(0)(0)(0)(0)
n = UInt(Rn); write_nzcvq = (mask == ‘1’); write_g = (mask == ‘1’);
if mask == ‘00’ then UNPREDICTABLE;
if n == 15 then UNPREDICTABLE;
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
MSR ,
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 0 1 0 0 1 0 mask 0 0 (1)(1)(1)(1)(0)(0)(0)(0) 0 0 0 0 Rn
n = UInt(Rn); write_nzcvq = (mask == ‘1’); write_g = (mask == ‘1’);
if mask == ‘00’ then UNPREDICTABLE;
if n == 15 then UNPREDICTABLE;
Assembler syntax
MSR ,
where:
See Standard assembler syntax fields on page A8-7.
Is one of:
• APSR_
• CPSR_.
ARM recommends the APSR forms in application level code. For more information, see The
Application Program Status Register (APSR) on page A2-14.
Is the general-purpose register to be transferred to .
Is one of nzcvq, g, or nzcvqg.
In the A and R profiles:
APSR_nzcvq is the same as CPSR_f
APSR_g is the same as CPSR_s
APSR_nzcvqg is the same as CPSR_fs.
Is a sequence of one or more of the following: s, f.
A8-210 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B