ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

10 Region is WriteThrough, Non-WriteAllocate
11 Region is Write-Back, Non-WriteAllocate.
Virtual Memory System Architecture (VMSA)
The meaning of the field with n = 6 is IMPLEMENTATION DEFINED and might differ from the
meaning given here. This is because the meaning of the attribute combination
{TEX[0] = 1, C = 1, B = 0} is IMPLEMENTATION DEFINED.
IRn, bits [2n+1:2n], for values of n from 0 to 7
Inner Cacheable property mapping for memory attributes n, if the region is mapped as
Normal Memory by the TRn entry in the PRRR, see c10, Primary Region Remap Register
(PRRR) on page B3-143. n is the value of the TEX[0], C and B bits, see Table B3-36 on
page B3-145. The possible values of this field are the same as those given for the ORn field.
The meaning of the field with n = 6 is IMPLEMENTATION DEFINED and might differ from the
meaning given here. This is because the meaning of the attribute combination
{TEX[0] = 1, C = 1, B = 0} is IMPLEMENTATION DEFINED.
For more information about the NMRR see Memory region attribute descriptions when TEX remap is
enabled on page B3-34.
Accessing the NMRR
To access the NMRR you read or write the CP15 registers with set to 0, set to c10, set to
c2, and set to 1. For example:
MRC p15,0,,c10,c2,1 ; Read CP15 Normal Memory Remap Register
MCR p15,0,,c10,c2,1 ; Write CP15 Normal Memory Remap Register
B3.12.38 CP15 c11, Reserved for TCM DMA registers
Some CP15 c11 register encodings are reserved for IMPLEMENTATION DEFINED DMA operations to and
from TCM, see Figure B3-23:
CRn opc1 CRm opc2
c11 {0-7} {c0-c8} {0-7}
c15 {0-7}
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Read-only Read/Write
Write-only
Access depends on the operation
Reserved for DMA operations for TCM access
Reserved for DMA operations for TCM access
Figure B3-23 Permitted CP15 c11 encodings
CP15 c11 encodings not shown in Figure B3-23 are UNPREDICTABLE, see Unallocated CP15 encodings on
page B3-69.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-147
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