ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

In v7 Debug, the format of the DBGDSCR is:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
(0)
RXfull
TXfull
RXfull_l
TXfull_l
PipeAdv
InstrCompl_l
(0)
† Reserved, UNK/SBZP
In ARMv6, bit [9] can
be DBGnoPWRDWN
Bits [31,28,23:22]
RXfull, bit [30]
(0) (0)
ExtDCCmode
ADAdiscard
SPNIDdis
SPIDdis
MDBGen
HDBGen
ITRen
UDCCdis
INTdis
DBGack
Reserved, UNK/SBZP.
NS
Debug Registers Reference
The DBGDTRRX Register full bit. The possible values of this bit are:
0 DBGDTRRX Register empty
1 DBGDTRRX Register full.
Normally, RXfull is:
set to 1 on writes to DBGDTRRXext
cleared to 0 on reads of DBGDTRRXint.
For more information about the behavior of RXfull and the DBGDTRRX Register see Host
to Target Data Transfer Register (DBGDTRRX) on page C10-40.
TXfull, bit [29]
The DBGDTRTX Register full bit. The possible values of this bit are:
0 DBGDTRTX Register empty
1 DBGDTRTX Register full.
Normally, TXfull is:
cleared to 0 on reads of DBGDTRTXext
set to 1 on writes to DBGDTRTXint.
For more information about the behavior of TXfull and the DBGDTRTX Register see Target
to Host Data Transfer Register (DBGDTRTX) on page C10-43.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-11
Res.†
MOE
2
SDABORT_l
ADABORT_l
UND_l
RESTARTED
HALTED
1
0