ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
v7 Debug The Extended CP14 interface instructions that access DBGDTRRXext, if implemented, are
UNPREDICTABLE in Debug state. For more information, see Internal and external views of
the DBGDSCR and the DCC registers on page C6-21 and Extended CP14 interface on
page C6-33.
The format of the DBGDTRRX Register is:
31 0
Host to target data
Host to target data, bits [31:0]
One word of data for transfer from the debug host to the debug target.
The debug logic reset value of the DBGDTRRX Register is UNKNOWN.
Access to the DBGDTRRX Register
The behavior on various accesses to the DBGDTRRX Register is described in the following tables:
Table C10-4 shows the behavior of accesses to DBGDTRRXint
Table C10-5 on page C10-42 shows the behavior of read accesses to DBGDTRRXext
Table C10-6 on page C10-42 shows the behavior of write accesses to DBGDTRRXext.
To access the DBGDTRRXint Register you read the CP14 registers using either:
an MRC instruction with set to 0, set to c0, set to c5, and set to 0
an STC instruction with set to c5.
Both instructions read only one word from the DBGDTRRXint Register. For example:
MCR p14,0,,c0,c5,0 ; Read DBGDTRRXint Register
STC p14,c5,[],#4 ; Read a word from the DBGDTRRXint Register and write it to memory
Note
Table C10-4 Behavior of accesses to DBGDTRRXint
Access RXfull Action New RXfull
Read 0 Returns an UNKNOWN value. Unchanged
1 Returns DBGDTRRX contents 0
Write X Not possible. There is no operation that writes to DBGDTRRXint -
If the STC instruction that reads DBGDTRRXint aborts, the contents of DBGDTRRX and the value
of the RXfull flag are UNKNOWN.
The behavior on accesses to DBGDTRRXint does not depend on the value of RXfull_l,
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. C10-41