ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Registers Reference
Table C10-11 Effect of byte address selection on Breakpoint generation
This BRP programmed for:
Instruction set a Instruction address b DBGBCR[8:5] IVA match IVA mismatch
Any Any address 0000 Miss Hit
ARM DBGBVR:’00’ 1111 Hit Miss
0000 Miss Hit
Any other value UNPREDICTABLE
Any other address xxxx Miss Hit
Thumb or ThumbEE DBGBVR:’00’ xx11 Hit Miss
xx10 UNPREDICTABLE
xx01 UNPREDICTABLE
xx00 Miss Hit
DBGBVR:’10’ 11xx Hit Miss
10xx UNPREDICTABLE
01xx UNPREDICTABLE
00xx Miss Hit
Any other address xxxx Miss Hit
Jazelle DBGBVR:’00’ xxx1 Hit Miss
xxx0 Miss Hit
DBGBVR:’01’ xx1x Hit Miss
xx0x Miss Hit
DBGBVR:’10’ x1xx Hit Miss
x0xx Miss Hit
C10-56 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B