ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

A6.2.5 Miscellaneous 16-bit instructions
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 Opcode
Thumb Instruction Set Encoding
Table A6-6 shows the allocation of encodings in this space. Other encodings in this space are UNDEFINED.
Table A6-6 Miscellaneous 16-bit instructions
Opcode Instruction See Variant
0110010 Set Endianness SETEND on page A8-314 v6
0110011 Change Processor State CPS on page B6-3 v6
00000xx Add Immediate to SP ADD (SP plus immediate) on page A8-28 v4T
00001xx Subtract Immediate from SP SUB (SP minus immediate) on page A8-426 v4T
0001xxx Compare and Branch on Zero CBNZ, CBZ on page A8-66 v6T2
001000x Signed Extend Halfword SXTH on page A8-444 v6
001001x Signed Extend Byte SXTB on page A8-440 v6
001010x Unsigned Extend Halfword UXTH on page A8-524 v6
001011x Unsigned Extend Byte UXTB on page A8-520 v6
0011xxx Compare and Branch on Zero CBNZ, CBZ on page A8-66 v6T2
010xxxx Push Multiple Registers PUSH on page A8-248 v4T
1001xxx Compare and Branch on Nonzero CBNZ, CBZ on page A8-66 v6T2
101000x Byte-Reverse Word REV on page A8-272 v6
101001x Byte-Reverse Packed Halfword REV16 on page A8-274 v6
101011x Byte-Reverse Signed Halfword REVSH on page A8-276 v6
1011xxx Compare and Branch on Nonzero CBNZ, CBZ on page A8-66 v6T2
110xxxx Pop Multiple Registers POP on page A8-246 v4T
1110xxx Breakpoint BKPT on page A8-56 v5
1111xxx If-Then, and hints If-Then, and hints on page A6-12 -
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A6-11