ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Protected Memory System Architecture (PMSA)
Sharing resources among applications requires a state saving mechanism. Two possibilities are:
during a context switch, if the last executing process or thread had access rights to a coprocessor then
the operating system saves the state of that coprocessor
on receiving a request for access to a coprocessor, the operating system saves the old state for that
coprocessor with the last process or thread that accessed it.
Accessing the CPACR
To access the CPACR you read or write the CP15 registers with set to 0, set to c1, set to
c0, and set to 2. For example:
MRC p15,0,,c1,c0,2 ; Read CP15 Coprocessor Access Control Register
MCR p15,0,,c1,c0,2 ; Write CP15 Coprocessor Access Control Register
Normally, software uses a read, modify, write sequence to update the CPACR, to avoid unwanted changes
to the access settings for other coprocessors.
B4.6.19 CP15 c2 and c3, Not used on a PMSA implementation
The CP15 c2 and c3 register encodings are not used on an ARMv7-R implementation, see Unallocated
CP15 encodings on page B4-27.
B4.6.20 CP15 c4, Not used
The CP15 c4 register encodings are not used on an ARMv7 implementation, see Unallocated CP15
encodings on page B4-27.
B4.6.21 CP15 c5 and c6, Memory system fault registers
The CP15 c5 and c6 registers are used for memory system fault reporting. In addition, c6 provides the MPU
Region registers. Figure B4-7 on page B4-54 shows the CP15 c5 and c6 registers.
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