ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

A9.5.5 LDR (immediate)
Load Register (immediate) provides 16-bit instructions to load words using:
R9 as base register, with a positive offset of up to 63 words, for loading from a frame
R10 as base register, with a positive offset of up to 31 words, for loading from a literal pool
R0-R7 as base register, with a negative offset of up to 7 words, for array operations.
Encoding E1 ThumbEE
LDR ,[R9{, #}]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 0 imm6 Rt
t = UInt(Rt); n = 9; imm32 = ZeroExtend(imm6:’00’, 32); add = TRUE;
Encoding E2 ThumbEE
LDR ,[R10{, #}]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 0 1 1 imm5 Rt
t = UInt(Rt); n = 10; imm32 = ZeroExtend(imm5:’00’, 32); add = TRUE;
Encoding E3 ThumbEE
LDR ,[{, #-}]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 0 0 imm3 Rn Rt
t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm3:’00’, 32); add = FALSE;
ThumbEE
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A9-19