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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Instruction Details<br />

A8.6.238 UHADD16<br />

Unsigned Halving Add 16 performs two unsigned 16-bit integer additions, halves the results, <strong>and</strong> writes the<br />

results to the destination register.<br />

Encoding T1 <strong>ARM</strong>v6T2, <strong>ARM</strong>v7<br />

UHADD16 ,,<br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

1 1 1 1 1 0 1 0 1 0 0 1 Rn 1 1 1 1 Rd 0 1 1 0 Rm<br />

d = UInt(Rd); n = UInt(Rn); m = UInt(Rm);<br />

if BadReg(d) || BadReg(n) || BadReg(m) then UNPREDICTABLE;<br />

Encoding A1 <strong>ARM</strong>v6*, <strong>ARM</strong>v7<br />

UHADD16 ,,<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

cond 0 1 1 0 0 1 1 1 Rn Rd (1)(1)(1)(1) 0 0 0 1 Rm<br />

d = UInt(Rd); n = UInt(Rn); m = UInt(Rm);<br />

if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;<br />

A8-470 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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