ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
If the translation fails without generating an abort, the format of the PAR is:
31 7 6 1 0
UNK/SBZP FS F
Bits [31:7] UNK/SBZP.
FS, bits [6:1] Fault status bits. Bits [12,10,3:0] from the Data Fault Status Register, indicate the source of
the abort. For more information, see c5, Data Fault Status Register (DFSR) on page B3-121.
F, bit [0] F bit is 1 if the conversion aborted.
The VA to PA translation only generates an abort if the translation fails because an external abort occurred
on a translation table walk request. In this case:
If the external abort is synchronous, the DFSR and DFAR of the security state in which the abort is
handled are updated. The DFSR indicates the appropriate external abort on Translation fault, and the
DFAR indicates the MVA that caused the translation. PAR is UNKNOWN.
If the external abort is asynchronous, the DFSR of the security state in which the abort is handled is
updated when the abort is taken. The DFSR indicates the asynchronous external abort. The DFAR is
not updated. PAR is UNKNOWN.
For all other cases where the VA to PA translation fails:
No abort is generated, and the DFSR and DFAR are unchanged
the PAR [6:1] field is updated with an FSR encoding that indicates the fault
the PAR bit [0] is set to 1.
Implementations that do not support all attributes can report the behavior for those memory types that the
cache does support.
Accessing the PAR and the VA to PA translation operations
To access one of the VA to PA translation operations you write the CP15 registers with set to 0,
set to c7, set to c8, and set to the value shown in Table B3-33 on page B3-131 or Table B3-34
on page B3-131.
With register Rt containing the original VA this gives:
MCR p15,0,,c7,c8,
To read the PAR you read the CP15 registers with set to 0, set to c7, set to c4, and
set to 0. To return the translated PA in register Rt this gives:
MRC p15,0,,c7,c4,0
The PAR is a read/write register, and you can write to the CP15 registers with the same settings to write to
the register. There is no translation operation that requires writing to this register, but the write operation
might be required to restore the value of the PAR after a context switch.
An example of a VA to PA translation when the Security Extensions are not implemented is:
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-135