ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug Register Interfaces
Sticky
Power- down
set
Conditions Registers:
OS Lock
set
DBGECR,
DBGDRCR,
DBGOSLAR a,
DBGOSLSR a ,
DBGPRCR,
DBGPRSR
Table C6-12 Access to Extended CP14 interface debug registers
DBGOSSRR a
Other
debug b
In v7 Debug the behavior of Extended CP14 interface MRC and MCR instructions also depends on the access
type of the register, as shown in Table C6-2 on page C6-18. Table C6-13 summarizes the behavior of these
instructions, for:
read accesses, using MRC p14,0,,,,
write accesses, using MCR p14,0,,,,.
Some read/write registers include bits that are read-only. These bits ignore writes.
All reserved c
No No OK UNPREDICTABLE OK UNPREDICTABLE OK
No Yes OK OK UNDEFINED UNPREDICTABLE OK
Yes X OK UNPREDICTABLE UNDEFINED UNPREDICTABLE OK
Other
mgmt d
a. If the OS Save and Restore mechanism is not implemented, these registers addresses behave as reserved locations.
b. Debug register numbers 0 to 127, except for the DBGECR, DBGDRCR, the registers defined as baseline registers, and
reserved registers. For details of the baseline registers see Table C6-4 on page C6-32.
c. See also Access to implementation defined and reserved registers on page C6-29.
d. Other management registers. This means debug register numbers 832 to 1023, except for the IMPLEMENTATION DEFINED
locations, see Access to implementation defined and reserved registers on page C6-29.
Table C6-13 Behavior of CP14 MRC and MCR instructions, v7 Debug
with Extended CP14 interface
Access type a
Read access b
Write access b
- (Reserved) UNPREDICTABLE UNPREDICTABLE
Read-only Returns register value in Rt UNPREDICTABLE
Write-only UNPREDICTABLE Writes value in Rt to register
Read/write Returns register value in Rt Writes value in Rt to register
a. Register access type, as shown in Table C6-2 on page C6-18.
b. In a privileged mode, or in Debug state.
C6-40 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B