ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Instruction Set Encoding
A5.4.1 Parallel addition and subtraction, signed
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 1 1 0 0 0 op1 op2 1
Table A5-17 shows the allocation of encodings in this space. These encodings are all available in ARMv6
and above, and are UNDEFINED in earlier variants of the architecture.
Other encodings in this space are UNDEFINED.
Table A5-17 Signed parallel addition and subtraction instructions
op1 op2 Instruction See
01 000 Add 16-bit SADD16 on page A8-296
01 001 Add and Subtract with Exchange SASX on page A8-300
01 010 Subtract and Add with Exchange SSAX on page A8-366
01 011 Subtract 16-bit SSUB16 on page A8-368
01 100 Add 8-bit SADD8 on page A8-298
01 111 Subtract 8-bit SSUB8 on page A8-370
Saturating instructions
10 000 Saturating Add 16-bit QADD16 on page A8-252
10 001 Saturating Add and Subtract with Exchange QASX on page A8-256
10 010 Saturating Subtract and Add with Exchange QSAX on page A8-262
10 011 Saturating Subtract 16-bit QSUB16 on page A8-266
10 100 Saturating Add 8-bit QADD8 on page A8-254
10 111 Saturating Subtract 8-bit QSUB8 on page A8-268
Halving instructions
11 000 Halving Add 16-bit SHADD16 on page A8-318
11 001 Halving Add and Subtract with Exchange SHASX on page A8-322
11 010 Halving Subtract and Add with Exchange SHSAX on page A8-324
11 011 Halving Subtract 16-bit SHSUB16 on page A8-326
11 100 Halving Add 8-bit SHADD8 on page A8-320
11 111 Halving Subtract 8-bit SHSUB8 on page A8-328
A5-22 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B