ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B4.3 Memory region attributes
Protected Memory System Architecture (PMSA)
Each memory region has an associated set of memory region attributes. These control accesses to the caches,
how the write buffer is used, and whether the memory region is Shareable and therefore is guaranteed by
hardware to be coherent. These attributes are encoded in the C, B, TEX[2:0] and S bits of the appropriate
Region Access Control Register.
Note
The Bufferable (B), Cacheable (C), and Type Extension (TEX) bit names are inherited from earlier versions
of the architecture. These names no longer adequately describe the function of the B, C, and TEX bits.
B4.3.1 C, B, and TEX[2:0] encodings
The TEX[2:0] field must be considered with the C and B bits to give a five bit encoding of the access
attributes for an MPU memory region. Table B4-4 shows these encodings.
For Normal memory regions, the S (Shareable) bit gives more information about whether the region is
Shareable. A Shareable region can be shared by multiple processors. A Normal memory region is Shareable
if the S bit for the region is set to 1. For other memory types, the value of the S bit is ignored.
Table B4-4 C, B and TEX[2:0] encodings
TEX[2:0] C B Description Memory type Shareable?
000 0 0 Strongly-ordered. Strongly-ordered Shareable
000 0 1 Shareable Device. Device Shareable
000 1 0 Outer and Inner Write-Through, no Write-Allocate. Normal S bit a
000 1 1 Outer and Inner Write-Back, no Write-Allocate. Normal S bit a
001 0 0 Outer and Inner Non-cacheable. Normal S bit a
001 0 1 Reserved. - -
001 1 0 IMPLEMENTATION DEFINED. IMP. DEF. b IMP. DEF. b
001 1 1 Outer and Inner Write-Back, Write-Allocate. Normal S bit a
010 0 0 Non-shareable Device. Device Non-shareable
010 0 1 Reserved. - -
010 1 X Reserved. - -
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B4-11