ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Glossary
Temporal locality
Is the observed effect that after a program has accesses a memory location, it is likely to access the same
memory location again in the near future. Caches exploit this effect to improve performance.
Thumb instruction
Is one or two halfwords that specify an operation for a processor in Thumb state to perform. Thumb
instructions must be halfword-aligned.
TLB See Translation Lookaside Buffer.
TLB lockdown
Is a way to prevent specific translation table walk results being accessed. This ensures that accesses to the
associated memory areas never cause a translation table walk.
Translation Lookaside Buffer (TLB)
Is a memory structure containing the results of translation table walks. They help to reduce the average cost
of a memory access. Usually, there is a TLB for each memory interface of the ARM implementation.
Translation tables
Are tables held in memory. They define the properties of memory areas of various sizes from 1KB to 1MB.
Translation table walk
Is the process of doing a full translation table lookup. It is performed automatically by hardware.
Trap enable bits
Determine whether trapped or untrapped exception handling is selected. If trapped exception handling is
selected, the way it is carried out is IMPLEMENTATION DEFINED.
Unaligned
An unaligned access is an access where the address of the access is not aligned to the size of an element of
the access.
Unaligned memory accesses
Are memory accesses that are not, or might not be, appropriately halfword-aligned, word-aligned, or
doubleword-aligned.
Unallocated
Except where otherwise stated, an instruction encoding is unallocated if the architecture does not assign a
specific function to the entire bit pattern of the instruction, but instead describes it as UNDEFINED,
UNPREDICTABLE, or an unallocated hint instruction.
A bit in a register is unallocated if the architecture does not assign a function to that bit.
UNDEFINED
Indicates an instruction that generates an Undefined Instruction exception.
See also Undefined Instruction exception on page B1-49.
Unified cache
Is a cache used for both processing instruction fetches and processing data loads and stores.
Glossary-12 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B