ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.333 VMOVL
Vector Move Long takes each element in a doubleword vector, sign or zero-extends them to twice their
original length, and places the results in a quadword vector.
Encoding T1 / A1 Advanced SIMD
VMOVL. ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 U 1 1 1 1 1 D imm3 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 U 1 D imm3 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm
if imm3 == ‘000’ then SEE “Related encodings”;
if imm3 != ‘001’ && imm3 != ‘010’ && imm3 != ‘100’ then SEE VSHLL;
if Vd == ‘1’ then UNDEFINED;
esize = 8 * UInt(imm3);
unsigned = (U == ‘1’); elements = 64 DIV esize;
d = UInt(D:Vd); m = UInt(M:Vm);
Related encodings See One register and a modified immediate value on page A7-21
A8-654 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B