ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
1 All instruction encodings identified in the Alphabetical list of instructions on
page A8-14 as being VFPv3 instructions are UNDEFINED if they access any of
registers D16-D31.
If this bit is 1 when CPACR.ASEDIS == 0, the result is UNPREDICTABLE.
On an implementation that:
Does not implement VFP, this bit is UNK/SBZP.
Implements VFP and does not implement D16-D31, this bit is RAO/WI.
Implements VFP and implements D16-D31, it is IMPLEMENTATION DEFINED whether
this bit is supported. If it is not, then this bit is RAZ/WI.
This bit resets to 0 if it is supported.
Bits [29:28] Reserved. UNK/SBZP.
cp, bits [2n+1, 2n], for n = 0 to 13
Defines the access rights for coprocessor n. The possible values of the field are:
0b00 Access denied. Any attempt to access the coprocessor generates an Undefined
Instruction exception.
0b01 Privileged access only. Any attempt to access the coprocessor in User mode
generates an Undefined Instruction exception.
0b10 Reserved. The effect of this value is UNPREDICTABLE.
0b11 Full access. The meaning of full access is defined by the appropriate
coprocessor.
The value for a coprocessor that is not implemented is 0b00, access denied.
When the Security Extensions are implemented, the NSACR controls whether each coprocessor can be
accessed from the Non-secure state, see c1, Non-Secure Access Control Register (NSACR) on page B3-110.
When the NSACR permits Non-secure access to a coprocessor the level of access permitted is determined
by the CPACR. Because the CPACR is not banked, the options for Non-secure state access to a coprocessor
are:
no access
identical access rights to the Secure state.
If more than one coprocessor is used to provide a set of functionality then having different values for the
CPACR fields for those coprocessors can lead to UNPREDICTABLE behavior. An example where this must be
considered is with the VFP extension. This uses CP10 and CP11.
Typically, an operating system uses this register to control coprocessor resource sharing among applications:
Initially all applications are denied access to the shared coprocessor-based resources.
When an application attempts to use a resource it results in an Undefined Instruction exception.
The Undefined Instruction handler can then grant access to the resource by setting the appropriate
field in the CPACR.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-105