ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.383 VSHL (register)
Vector Shift Left (register) takes each element in a vector, shifts them by a value from the least significant
byte of the corresponding element of a second vector, and places the results in the destination vector. If the
shift value is positive, the operation is a left shift. If the shift value is negative, it is a truncating right shift.
(For a rounding shift, see VRSHL on page A8-736).
The first operand and result elements are the same data type, and can be any one of:
8-bit, 16-bit, 32-bit, or 64-bit signed integers
8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.
The second operand is always a signed integer of the same size.
Encoding T1 / A1 Advanced SIMD
VSHL.I , ,
VSHL.I , ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 U 1 1 1 1 0 D size Vn Vd 0 1 0 0 N Q M 0 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 0 0 N Q M 0 Vm
if Q == ‘1’ && (Vd == ‘1’ || Vm == ‘1’ || Vn == ‘1’) then UNDEFINED;
unsigned = (U == ‘1’);
esize = 8