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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Debug Register Interfaces<br />

The performance monitor registers described in Chapter C9 Performance Monitors.<br />

The trace registers.<br />

The OS Restore sequence always overwrites the debug registers with the values that were saved. In<br />

particular, the values of the DBGDTRTX <strong>and</strong> DBGDTRRX Registers, <strong>and</strong> of the DCC status flags TXfull,<br />

TXfull_l, RXfull, <strong>and</strong> RXfull_l after the OS Restore sequence are the saved values.<br />

If there were valid values in the DBGDTRTX or DBGDTRRX Registers immediately before the OS Restore<br />

sequence then those values are lost.<br />

Example OS Save <strong>and</strong> Restore sequences<br />

Example OS Save <strong>and</strong> Restore sequences are described in:<br />

Example OS Save <strong>and</strong> Restore sequences using the memory-mapped interface<br />

Example OS Save <strong>and</strong> Restore sequences using the Extended CP14 interface on page C6-14.<br />

Example OS Save <strong>and</strong> Restore sequences using the memory-mapped interface<br />

On an implementation that includes the OS Save <strong>and</strong> Restore mechanism <strong>and</strong> a memory-mapped interface:<br />

Example C6-1 shows the correct sequence for saving the debug logic state, using the<br />

memory-mapped interface, before powering down<br />

Example C6-2 on page C6-13 shows the correct sequence for restoring the debug logic state, using<br />

the memory-mapped interface, when the system is powered on again.<br />

When the debug logic state is restored, if the OS Unlock Catch bit in the Event Catch Register is set to 1 a<br />

debug event is triggered when the DBGOSLAR is cleared. This event might be used by an external debugger<br />

to restart a debugging session. See Event Catch Register (DBGECR) on page C10-78.<br />

Example C6-1 OS debug register save sequence, memory-mapped interface<br />

; On entry, R0 points to a block to save the debug registers in.<br />

SaveDebugRegisters<br />

PUSH {R4, LR}<br />

MOV R4, R0 ; Save pointer<br />

; (1) Set OS Lock Access Register (DBGOSLAR). The architecture requires that DBGOSLAR<br />

; <strong>and</strong> the other debug registers have at least the Device memory attribute.<br />

BL GetDebugRegisterBase ; Returns base in R0<br />

LDR R1, =0xC5ACCE55<br />

STR R1, [R0, #0x300] ; Write DBGOSLAR<br />

; (2) Get the number of words to save.<br />

LDR R1, [R0, #0x308] ; DBGOSSRR returns size<br />

STR R1, [R4], #4 ; Push on to the save stack<br />

; (3) Loop reading words from the DBGOSSRR.<br />

C6-12 Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. <strong>ARM</strong> DDI 0406B

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