ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

A6.3.15 Miscellaneous operations
Thumb Instruction Set Encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 1 0 1 0 op1 1 1 1 1 1 0 op2
If, in the second halfword of the instruction, bits [15:12] != 0b1111, the instruction is UNDEFINED.
Table A6-26 shows the allocation of encodings in this space. Other encodings in this space are UNDEFINED.
These encodings are all available in ARMv6T2 and above.
op1 op2 Instruction See
Table A6-26 Miscellaneous operations
00 00 Saturating Add QADD on page A8-250
01 Saturating Double and Add QDADD on page A8-258
10 Saturating Subtract QSUB on page A8-264
11 Saturating Double and Subtract QDSUB on page A8-260
01 00 Byte-Reverse Word REV on page A8-272
01 Byte-Reverse Packed Halfword REV16 on page A8-274
10 Reverse Bits RBIT on page A8-270
11 Byte-Reverse Signed Halfword REVSH on page A8-276
10 00 Select Bytes SEL on page A8-312
11 00 Count Leading Zeros CLZ on page A8-72
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A6-37