ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VCVT{R}.S32.F64 , opc2 = ’101’, sz = 1
VCVT{R}.S32.F32 , opc2 = ’101’, sz = 0
VCVT{R}.U32.F64 , opc2 = ’100’, sz = 1
VCVT{R}.U32.F32 , opc2 = ’100’, sz = 0
VCVT.F64. , opc2 = ’000’, sz = 1
VCVT.F32. , opc2 = ’000’, sz = 0
where:
Instruction Details
R If R is specified, the operation uses the rounding mode specified by the FPSCR. Encoded as
op = 0.
If R is omitted. the operation uses the Round towards Zero rounding mode. For syntaxes in
which R is optional, op is encoded as 1 if R is omitted.
See Standard assembler syntax fields on page A8-7.
The data type for the operand. It must be one of:
S32 encoded as op = 1
U32 encoded as op = 0.
, The destination register and the operand register, for a double-precision operand.
, The destination register and the operand register, for a double-precision result.
, The destination register and the operand register, for a single-precision operand or result.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
if to_integer then
if dp_operation then
S[d] = FPToFixed(D[m], 32, 0, unsigned, round_zero, TRUE);
else
S[d] = FPToFixed(S[m], 32, 0, unsigned, round_zero, TRUE);
else
if dp_operation then
D[d] = FixedToFP(S[m], 64, 0, unsigned, round_fpscr, TRUE);
else
S[d] = FixedToFP(S[m], 32, 0, unsigned, round_fpscr, TRUE);
Exceptions
Undefined Instruction.
Floating-point exceptions: Input Denormal, Invalid Operation, and Inexact.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-579