ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.365 VQRSHRN, VQRSHRUN
Vector Saturating Rounding Shift Right, Narrow takes each element in a quadword vector of integers, right
shifts them by an immediate value, and places the rounded results in a doubleword vector.
For truncated results, see VQSHRN, VQSHRUN on page A8-722.
The operand elements must all be the same size, and can be any one of:
16-bit, 32-bit, or 64-bit signed integers
16-bit, 32-bit, or 64-bit unsigned integers.
The result elements are half the width of the operand elements. If the operand elements are signed, the
results can be either signed or unsigned. If the operand elements are unsigned, the result elements must also
be unsigned.
If any of the results overflow, they are saturated. The cumulative saturation flag, QC, is set if saturation
occurs. For details see Pseudocode details of saturation on page A2-9.
Encoding T1 / A1 Advanced SIMD
VQRSHR{U}N. ,,#
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 U 1 1 1 1 1 D imm6 Vd 1 0 0 op 0 1 M 1 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 U 1 D imm6 Vd 1 0 0 op 0 1 M 1 Vm
if imm6 == ‘000xxx’ then SEE “Related encodings”;
if U == ‘0’ && op == ‘0’ then SEE VRSHRN;
if Vm == ‘1’ then UNDEFINED;
case imm6 of
when ‘001xxx’ esize = 8; elements = 8; shift_amount = 16 - UInt(imm6);
when ‘01xxxx’ esize = 16; elements = 4; shift_amount = 32 - UInt(imm6);
when ‘1xxxxx’ esize = 32; elements = 2; shift_amount = 64 - UInt(imm6);
src_unsigned = (U == ‘1’ && op == ‘1’); dest_unsigned = (U == ‘1’);
d = UInt(D:Vd); m = UInt(M:Vm);
Related encodings See One register and a modified immediate value on page A7-21
A8-716 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B