ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.401 VSUB (integer)
Vector Subtract subtracts the elements of one vector from the corresponding elements of another vector, and
places the results in the destination vector.
Encoding T1 / A1 Advanced SIMD
VSUB. , ,
VSUB. , ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 0 D size Vn Vd 1 0 0 0 N Q M 0 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 0 D size Vn Vd 1 0 0 0 N Q M 0 Vm
if Q == ‘1’ && (Vd == ‘1’ || Vn == ‘1’ || Vm == ‘1’) then UNDEFINED;
esize = 8