ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.303 VDUP (ARM core register)
This instruction duplicates an element from an ARM core register into every element of the destination
vector.
The destination vector elements can be 8-bit, 16-bit, or 32-bit bitfields. The source element is the least
significant 8, 16, or 32 bits of the ARM core register. There is no distinction between data types.
Encoding T1 / A1 Advanced SIMD
VDUP. ,
VDUP. ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 1 0 1 b Q 0 Vd Rt 1 0 1 1 D 0 e 1 (0)(0)(0)(0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 1 0 1 b Q 0 Vd Rt 1 0 1 1 D 0 e 1 (0)(0)(0)(0)
if Q == ‘1’ && Vd == ‘1’ then UNDEFINED;
d = UInt(D:Vd); t = UInt(Rt); regs = if Q == ‘0’ then 1 else 2;
case b:e of
when ‘00’ esize = 32; elements = 2;
when ‘01’ esize = 16; elements = 4;
when ‘10’ esize = 8; elements = 8;
when ‘11’ UNDEFINED;
if t == 15 || (CurrentInstrSet() != InstrSet_ARM && t == 13) then UNPREDICTABLE;
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