ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
SCTLR.TRE, SCTLR.M, and the effect of the MMU remap registers
When TEX remap is disabled, because the SCTLR.TRE bit is set to 0:
the effect of the MMU remap registers can be IMPLEMENTATION DEFINED
the interpretation of the fields of the PRRR and NMRR registers can differ from the description given
in this section.
VMSAv7 requires that the effect of these registers is limited to remapping the attributes of memory
locations. These registers must not change whether any cache or MMU hardware is enabled. The
mechanism by which the MMU remap registers have an effect when the SCTLR.TRE bit is set to 0 is
IMPLEMENTATION DEFINED. The ARMv7 architecture requires that from reset, if the IMPLEMENTATION
DEFINED mechanism has not been invoked:
If the MMU is enabled, the architecturally-defined behavior of the TEX[2:0], C, and B bits must
apply, without reference to the TEX remap functionality. In other words, memory attribute
assignment must comply with the scheme described in C, B, and TEX[2:0] encodings without TEX
remap on page B3-33.
If the MMU is disabled, then the architecturally-defined behavior of the VMSA with the MMU
disabled must apply, without reference to the TEX remap functionality. See Enabling and disabling
the MMU on page B3-5.
Typical mechanisms for enabling the IMPLEMENTATION DEFINED effect of the TEX Remap registers when
SCTLR.TRE bit is set to 0 include:
a control bit in the ACTLR, or in a CP15 c15 register
changing the behavior when the PRRR and NMRR registers are changed from their
IMPLEMENTATION DEFINED reset values.
In addition, if the MMU is disabled and the SCTLR.TRE bit is set to 1, the architecturally-defined behavior
of the VMSA with the MMU disabled must apply without reference to the TEX remap functionality.
When the Security Extensions are implemented, the IMPLEMENTATION DEFINED effect of these registers
must only take effect in the security domain of the registers.
The OS managed translation table bits
When TEX remap is enabled, the TEX[2:1] bits in the translation table descriptors are available as two flags
that can be managed by the operating system. In VMSAv7, as long as the SCTLR.TRE bit is set to 1, the
values of the TEX[2:1] bits are ignored by the memory management hardware. You can write any value to
these bits in the translation tables. In a system that implements access flag updates in hardware, a hardware
access flag update never changes these bits.
B3-38 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B