ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

implement one of the other permitted alternatives for the locked entries.
Common Memory System Architecture Features
ARM recommends that, where possible, architecturally-defined operations are used in such code sequences.
This minimizes the number of customized operations required.
In addition, any implementation that uses aborts for handling cache maintenance operations on entries that
might be locked must provide a mechanism that can be used to ensures that no entries are locked in the
cache. The reset setting of the cache must be that no cache entries are locked.
On an ARMv7-A implementation, similar rules apply to TLB lockdown, see The interaction of TLB
maintenance operations with TLB lockdown on page B3-57.
Additional cache functions for the implementation of lockdown
An implementation can add additional cache maintenance functions for the handling of lockdown in the
IMPLEMENTATION DEFINED spaces reserved for Cache Lockdown. Examples of possible functions are:
Operations that unlock all cache entries.
Operations that preload into specific levels of cache. These operations might be provided for
instruction caches, data caches, or both.
An implementation can add other functions as required.
B2.2.6 Branch predictors
Branch predictor hardware typically uses a form of cache to hold branch information. The ARM architecture
permits this branch predictor hardware to be visible to the functional behavior of software, and so the branch
predictor is not architecturally invisible. This means that under some circumstances software must perform
branch predictor maintenance to avoid incorrect execution caused by out of date entries in the branch
predictor.
Branch prediction maintenance operations
In some implementations, to ensure correct operation it might be necessary to invalidate branch prediction
entries on a change of instruction or instruction address mapping. For more information, see Branch
predictor maintenance operations and the memory order model on page B2-20.
Two CP15 c7 operations apply to branch prediction hardware, these two functions are:
MCR p15, 0, Rt, c7, c5, 6: Invalidate entire branch predictor array
MCR p15, 0, Rt, c7, c5, 7: Invalidate MVA from branch predictor array
In ARMv7, these functions can perform a NOP if the operation of Branch Prediction hardware is not visible
architecturally.
The invalidate entire branch predictor array operation ensures that any location held in the branch predictor
has no functional effect on execution.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B2-19