ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

A7.4.5 Two registers, miscellaneous
Advanced SIMD and VFP Instruction Encoding
Thumb encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 1 1 1 A 0 B 0
ARM encoding
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 1 1 A 0 B 0
The allocation of encodings in this space is shown in Table A7-13. Other encodings in this space are
UNDEFINED.
A B Instruction See
Table A7-13 Instructions with two registers, miscellaneous
00 0000x Vector Reverse in doublewords VREV16, VREV32, VREV64 on page A8-732
0001x Vector Reverse in words VREV16, VREV32, VREV64 on page A8-732
0010x Vector Reverse in halfwords VREV16, VREV32, VREV64 on page A8-732
010xx Vector Pairwise Add Long VPADDL on page A8-688
1000x Vector Count Leading Sign Bits VCLS on page A8-566
1001x Vector Count Leading Zeros VCLZ on page A8-570
1010x Vector Count VCNT on page A8-574
1011x Vector Bitwise NOT VMVN (register) on page A8-670
110xx Vector Pairwise Add and Accumulate Long VPADAL on page A8-682
1110x Vector Saturating Absolute VQABS on page A8-698
1111x Vector Saturating Negate VQNEG on page A8-710
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A7-19