ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Common VFP Subarchitecture Specification
FPEXC.TFV == 1
This bit is the Invalid Operation trapped exception flag. It indicates whether an
Invalid Operation exception occurred while FPSCR.IOE was 1.
In this case, the meaning of this bit is:
0 Invalid Operation exception has not occurred.
1 Invalid Operation exception has occurred.
In both cases this bit must be cleared to 0 by the exception handling routine.
B.6.2 The Floating-Point Instruction Registers, FPINST and FPINST2
The Floating-Point Instruction Registers hold floating-point instructions relating to floating-point exception
handling in a system that implements the Common VFP subarchitecture:
FPINST contains the exception-generating instruction
FPINST2 contains the bypassed instruction.
FPINST and FPINST2 are:
In the CP10 and CP11 register space.
Present only when the Common VFP subarchitecture is implemented. A Common VFP
subarchitecture implementation can support:
— both FPINST and FPINST2
— FPINST but not FPINST2
— neither of the Floating-Point Instruction Registers.
32-bit read/write registers.
If the Security Extensions are implemented, Configurable access registers. FPINST and FPINST2 are
only accessible in the Non-secure state if the CP10 and CP11 bits in the NSACR are set to 1, see c1,
Non-Secure Access Control Register (NSACR) on page B3-110.
Accessible only in privileged modes, and only if both:
— access to coprocessors CP10 and CP11 is enabled in the Coprocessor Access Control Register,
see c1, Coprocessor Access Control Register (CPACR) on page B3-104 (VMSA
implementation), or c1, Coprocessor Access Control Register (CPACR) on page B4-51
(PMSA implementation)
— the VFP coprocessor is enabled by setting the FPEXC.EN bit to 1.
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