ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

A6.3.7 Load word
Thumb Instruction Set Encoding
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 op1 1 0 1 Rn op2
Table A6-18 shows the allocation of encodings in this space. Other encodings in this space are UNDEFINED.
These encodings are all available in ARMv6T2 and above.
op1 op2 Rn Instruction See
Table A6-18 Load word
01 - not 1111 Load Register LDR (immediate, Thumb) on page A8-118
00 1xx1xx not 1111
1100xx not 1111
1110xx not 1111 Load Register Unprivileged LDRT on page A8-176
000000 not 1111 Load Register LDR (register) on page A8-124
0x - 1111 Load Register LDR (literal) on page A8-122
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A6-25